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Heterojunction bipolar transistor structure with high current gain and processing method thereof

A technology of bipolar transistors and processing methods, which can be applied to circuits, electrical components, semiconductor devices, etc., and can solve problems such as current gain drop

Inactive Publication Date: 2013-12-18
WIN SEMICON
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  • Claims
  • Application Information

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Problems solved by technology

In general, in order to improve the device characteristics of the transistor, the resistivity of the collector electrode 119 must be reduced, usually by increasing the n-type doping concentration of the sub-collector layer 107 (usually the doping impurity is silicon Si), but As the doping concentration increases, the epitaxial defect density of the sub-collector layer 107 also increases, resulting in a decrease in current gain.

Method used

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  • Heterojunction bipolar transistor structure with high current gain and processing method thereof
  • Heterojunction bipolar transistor structure with high current gain and processing method thereof
  • Heterojunction bipolar transistor structure with high current gain and processing method thereof

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Embodiment Construction

[0029] Figure 4 It is a schematic cross-sectional view of the epitaxial layer structure of the improved structure of the heterojunction bipolar transistor of the present invention, which includes a substrate 201, a p-type doped buffer layer 203, a primary collector layer 207, a collector layer 209, and a The base layer 211, an emitter layer 213, a collector electrode 219, a base electrode 221, and an emitter electrode 223.

[0030] In the structure of the present invention, the substrate 201 may generally be a semi-insulating gallium arsenide (GaAs) substrate. The p-type doped buffer layer 203 is formed on the substrate 201 by epitaxial growth technology. Existing epitaxial growth technologies include Molecular Beam Epitaxy (MBE) technology or Metal-organic Chemical Vapor Deposition (MOCVD) technology. The p-type doped buffer layer material can be gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (InGaP), indium aluminum phosphide (InAlP), in...

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Abstract

The invention discloses a heterojunction bipolar transistor improved structure with high current gain and a processing method of the heterojunction bipolar transistor improved structure. The improved structure comprises a substrate, a p type doped buffer layer, a primary collector layer, a collector layer, a base layer, an emitter layer, an emitter covering later and an emitter contact layer. A base electrode contact area is etched though multi-channel etching processing, the etching processing is stopped on the base layer, a collector electrode contact area is etched in the base electrode contact area, and the etching processing is stopped on a secondary collector layer. In the base electrode contact area, a base electrode is arranged on the base layer. A collector electrode is arranged in the collector electrode contact area and on the collector layer. An emitter electrode is then arranged on the emitter layer.

Description

Technical field [0001] The invention relates to an improved structure of a heterojunction bipolar transistor and its processing method, in particular to a p-type doped buffer layer between the collector layer and the substrate of the heterojunction bipolar transistor, Improved structure and processing method of heterojunction bipolar transistor capable of achieving high current gain properties. Background technique [0002] High current gain Heterojunction Bipolar Transistor (HBT) has the advantages of high efficiency, high linearity, high power density and small area. It is often used in wireless communications as a microwave power amplifier, which is very important in the communications electronics market. One of the important components. [0003] figure 1 It is a schematic cross-sectional view of the epitaxial layer structure of a conventional heterojunction bipolar transistor. The epitaxial layer structure is formed on a substrate 101 and includes a primary collector layer 10...

Claims

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Application Information

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IPC IPC(8): H01L29/737H01L29/06H01L21/331
Inventor 萧宏彬谢长霖
Owner WIN SEMICON
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