Through-silicon-via technique based three-dimensional band-pass filter

Although this design method can reduce the size of capacitors and low-pass filters, there are still some shortcomings: First, the coaxial silicon vias used in this patent belong to a non-standard silicon via structure, and its structure includes the first dielectric layer, The outer metal layer, the second dielectric layer and the metal core layer are electrically isolated by filling the first dielectric layer between the silicon substrate and the outer metal layer, and filling the second dielectric layer between the outer metal layer and the metal core layer. The outer metal layer must Grounding, when used as a capacitor design and application, the metal core layer is used as the upper plate electrode of the capacitor, and the outer metal layer is used as the lower plate electrode of the capacitor. This structure determines that the coaxial TSV capacitor is only suitable for grounding capacitor design and cannot be used for coupling Capacitors and band-pass filter designs including coupling capacitors; second, although the low-pass filter has excellent electromagnetic characteristics of coaxial TSVs, its structure is complex and the manufacturing cost is high, so it is not used in mainstream TSVs. It is widely used in packaging technology; thirdly, the inductance density and size of the inductor are the key factors affecting the size of the filter, but the low-pass filter still adopts the traditional planar inductor structure, and its inductance density is low. Experiment (N.Sturcken, et al., A 2.5D integrated voltage regulator using coupled magnetic-core inductors on silicon interposers, IEEE J.Solid-State Circuit, vol.48, no.1, pp.244-254, Jan.2013. ) and simulation data show that the inductance density of the planar spiral inductor is only 40~50nH / mm 2

These redundant through-silicon vias are inserted to meet these design rules. They are not used for effective electrical and thermal conduction in the chip, but they cause additional overhead for the silicon chip area.