High-reliability navigation sensor single event upset resisting device based on FPGA

[0022] The present invention will be further elaborated below by describing a preferred specific embodiment in detail in conjunction with the accompanying drawings.

[0023] Such as figure 1 As shown, a highly reliable navigation sensor anti-single event reversal logic circuit based on FPGA includes: a monitoring unit, which is used to monitor the number of signal transition edges; a first identification output unit, whose input terminal is connected to the monitoring unit , for outputting a first abnormal identification signal when the number of signal transition edges is less than a preset threshold during the preset duration of the monitoring window; the control unit, whose input end is connected to the identification output unit, is used for according to the described The first abnormal identification signal stops feeding the watchdog chip.

[0024] The monitoring unit is also used to monitor whether the signal is constant within the preset time period of the monitoring w...