49results about How to "Fewer pins" patented technology

An apparatus and method that correct skew associated with data receive from different transmission links. A known training pattern is sent through the transmission links. The training pattern is recovered and forwarded through delay registers / selecter logic to a memory buffer. A programmed controller accesses the memory and searches for the training pattern. If the training pattern is found for each transmission link, the offsets between the transmission links are determined and are used by the delay registers / selecter logic to adjust the position of the pattern so that the patterns from each link is linearly aligned within the memory buffer.

A method and apparatus for connecting low pin count (LPC, hereinafter) bus and serial flash memory is provided for converting the interface between a LPC bus and a serial flash memory in personal computer systems. The method according to the present invention comprises following procedures. First, a LPC bus instruction is fetched and converted to a serial instruction according to the required format of serial flash memory. The serial instruction is outputted to a serial flash memory. Next, an output data is read from the serial flash memory and converted to the required format according to the LPC bus. Lastly, the output data is outputted to the LPC bus.

The invention discloses a full-automatic collecting liquid-plastic limit combined measuring system. The full-automatic collecting liquid-plastic limit combined measuring system comprises a liquid-plastic limit combined measuring instrument and a computer, wherein the liquid-plastic limit combined measuring instrument comprises a mounting frame, a cone head, an electromagnet, a displacement transducer, a displacement display screen, a CPU (central processing unit), a communication module, a control switch and a specimen cup; the specimen cup is placed on the mounting frame; the electromagnet, the displacement transducer, the displacement display screen, the CPU, the communication module and the control switch are arranged on the mounting frame; the cone head is arranged above the opening of the specimen cup and is adsorbed on the electromagnet; the displacement transducer is connected with the computer in a signal manner through the CPU and the communication module; and a double logarithmic chart is stored in the computer. The full-automatic collecting liquid-plastic limit combined measuring system provided by the invention can be used for acquiring, measuring and reading data in a full automatic manner and drawing a curve, so that the accuracy of the test data is improved, the work amount of experimenters is reduced, the cost of human resources is reduced, and the test efficiency is improved.

The invention provides an automatic dehumidifier based on a moisture absorption sponge, and is used for improving air dehumidification efficiency. The dehumidifier mainly comprises a control unit, a signal acquisition unit, a dehydration unit, a dehumidifying water absorption unit and a power supply circuit unit; the signal acquisition unit mainly comprises a temperature and humidity sensor and aliquid level sensor, wherein the temperature and humidity sensor is used for detecting temperature and humidity of air, and the liquid level sensor is used for detecting water quantity of a water storage tank; the dehydration unit mainly comprises a dehumidifying bin, a dehumidifying sponge, a pressing plate, a driving mechanism and the water storage tank, wherein the pressing plate and the dehumidifying sponge are arranged in the dehumidifying bin, the driving mechanism for driving the pressing plate to ascend and descend is arranged at the upper part of the dehumidifying bin, the bottom partof the dehumidifying bin communicates with the water storage tank, and a gravity sensor is arranged in the dehumidifying bin; the dehumidifying water absorption unit is the dehumidifying sponge; andthe power supply circuit unit is used for providing power supply for the control unit, the temperature and humidity sensor, the liquid level sensor, the gravity sensor and an electromagnetic valve. According to the automatic dehumidifier, dehumidification operation can be efficiently realized.

A method and apparatus for connecting low pin count (LPC, hereinafter) bus and serial flash memory is provided for converting the interface between a LPC bus and a serial flash memory in personal computer systems. The method according to the present invention comprises following procedures. First, a LPC bus instruction is fetched and converted to a serial instruction according to the required format of serial flash memory. The serial instruction is outputted to a serial flash memory. Next, an output data is read from the serial flash memory and converted to the required format according to the LPC bus. Lastly, the output data is outputted to the LPC bus.

Disclosed is a method of taking electric power from a low voltage bypass for providing low voltage power supply for an integrated circuit. Also provided is an alternating current (AC) directly driven LED integrated circuit adapted to use the method; the integrated circuit includes a voltage stabilizing circuit, a low voltage electronic switch circuit, an under-voltage control circuit, and a comparative amplification circuit, and has three pins, a positive power supply terminal, a zero potential reference terminal, and a common terminal for current sampling and for the low voltage electronic switch. The method of taking electric power from a low voltage bypass for providing low voltage power supply for an AC directly driven LED integrated circuit, and the integrated circuit adapted to use the method have the advantages of low power consumption and cost, high efficiency and reliability, and fewer pins and external devices, and are easy to use.

The invention provides a system and a method for debugging multiple field-programmable gate arrays (FPGAs). The method comprises the following steps: selecting and grouping to-be-tested signals according to a clock domain by virtue of a signal selection and transmission module for instantiating each to-be-tested FPGA, and configuring a high-speed serial transceiver bus port of signal transmission; performing logic synthesis and location wiring on the design logic of the to-be-tested FPGAs and the signal selection and transmission module together; finding displacement information aligned with all channels according to the longest time delay in high-speed serial bus channels of all the to-be-tested FPGAs by using a special tested FPGA in a channel alignment operating mode selected by a debugging host; and selecting a to-be-tested signal group of the to-be-tested FPGA by the debugging host, and configuring the channel time delay value by using frequency information of the to-be-tested signal group. According to the system and the method disclosed by the invention, the cross-FPGA chip signal is observed and captured by using a special tested FPGA, and the fault tracing and positioning efficiency of a debugging system is improved.

A method and apparatus for burn-in of semiconductor devices is disclosed. A semiconductor device that includes built-in self test circuitry is coupled to a socket on a burn-in board. The burn in board and the semiconductor device are heated. Burn-in instructions can be transmitted to the semiconductor device through a JTAG terminal of the semiconductor device. Upon receiving a burn-in instruction through a JTAG terminal, the built-in self test circuitry is operable to perform one or more burn-in function. This allows for burn-in of a semiconductor device without any transfer of data through the data input terminals of the semiconductor device.

The invention discloses a drive circuit of a fluorescent tube, which comprises a resonance module, a tube module, a detection device and a controller, wherein the resonance module comprises a primary side and a secondary side so as to convert the electric power of input voltage received by the primary side into an AC signal and output the AC signal from the secondary side; the resonance module also comprises a transformer, and a primary side of the transformer is provided with two connecting ends and a central tap end; the tube module comprises a plurality of tubes and is coupled to the secondary side of the resonance module so as to receive the AC signal; the detection device and the tube module are connected in series to the secondary side of the resonance module; one end of the detection device is connected with a reference potential end, and the detection device generates a current detection signal and a protection feedback signal according to current flowing through the tubes; the controller comprises two semiconductor switches which are mutually connected through one end of each semiconductor switch, and the other ends are respectively coupled to the two connecting ends of the primary side of the transformer; a base pin of the controller receives the current detection signal so as to achieve feedback control, while the other base pin receives the protection feedback signal so as to achieve protection control, thereby simplifying the circuit design.

Techniques are provided for synchronously transmitting data in parallel from an external memory device to a destination circuit using a sequential read mode. The memory device includes an address counter. The address counter generates sequential read addresses for the data bits stored in the memory device. The destination circuit generates a clock signal that controls the address counter. The destination circuit can also transmit a start address to the memory device. The address counter sequentially generates a new read address in response to transitions in the clock signal beginning with the start address. Data bits are transferred in parallel from the memory device to the destination circuit.

The invention discloses a low-noise voltage-controlled oscillator biasing circuit and a frequency source self-calibration method. A voltage division circuit comprises a resistor R1, a first bipolar junction transistor BJT1 and a second bipolar junction transistor BJT2 which are connected in series in sequence, wherein the R1 is connected with the collector of the BJT1; the emitter of the BJT1 is connected with the collector of the BJT2; the collector of the BJT1 is connected with the base of the BJT1; and the collector of the BJT2 is connected with the base of the BJT2. In a self-calibration state, voltage output by the biasing circuit is connected with the tuning voltage input end and the power supply end of an LC voltage-controlled oscillator respectively. The output noise of the biasing circuit disclosed by the invention is low, a filter capacitor does not need to be added externally, the pins of a chip can be effectively reduced, and the cost is reduced; and when a frequency source is in the self-calibration state, the voltage output by the biasing circuit is connected with the tuning voltage input end and the power supply end of the LC voltage-controlled oscillator respectively, so that influences caused by the change of an output DC (Direct-Current) point due to changes of the resistor and the BJTs in a whole temperature range can be effectively eliminated, and change of the frequency source along with temperature change in the self-calibration state is avoided.

A high accurate A / D conversion circuit connects its all signal leading out wires to FPGA programmable logic circuit. The prepared circuit has high accuracy of A / D conversion with conversion cipher of 24 position, S - N ratio of 117 dB and dynamic range of 117 dB since it applies serial output after A / D conversion is finished.

The invention provides a charge pump sharing a flying capacitor. The charge pump comprises a voltage conversion module, wherein a first switch, a capacitor and a sixth switch of the voltage conversion module are connected in sequence between an anode of a power supply and a second output end, and a cathode of the power supply is connected with a ground node; one end of a third switch is connected with the anode of the power supply, and the other end of the third switch is connected with a node between the capacitor and the sixth switch; one end of a second switch is connected with the ground node, and the other end of the second switch is connected with the node between the capacitor and the sixth switch; one end of a fourth switch is connected with a node between the first switch and the capacitor, and the other end of the fourth switch is connected with a first output end; one end of a fifth switch is connected with the node between the first switch and the capacitor, and the other end of the fifth switch is connected with the ground node; a first output module is connected between the first output end and the ground node; a second output module is connected between the second output end and the ground node; a drive module is used for controlling switch-on or switch-off of each switch. A plurality of charge pumps share the same set of flying capacitors at different time segments, so that the number of flying capacitors is reduced.

The invention discloses an overhead transmission method, apparatus and device, and a computer readable storage medium, and belongs to the technical field of communications, the method comprising: extracting overhead data, and caching the overhead data as an overhead frame, the overhead frame comprising a channel number, a line number and overhead data; packaging the overhead frame into a custom overhead data frame; and performing serial transmission of overhead data according to the type of the custom overhead data frame. By adding identifiers such as channel numbers and row numbers before expenditure, caching in sequence and packaging into a custom packet for serial transmission of OTN expenditure, cross-FPGA insertion and extraction of expenditure are realized, the structure is simple, the portability is high, and OTN device pins are greatly saved.

A numerical controller includes a multicore processor, an integrated peripheral control LSI, a motor control section and an amplifier interface section. The multicore processor has two cores. One is assigned as a numerical control section processor core, and the other is assigned as a programmable machine controller section processor core. The motor control section is composed of a motor control section processor and a peripheral control LSI.

The invention discloses a line scanning driving method and a platform for a display screen. The driving method particularly comprises the following steps: scanning output signals are subjected to coding, and then the coded signals are subjected to primary digital decoding; the digital signals subjected to digital decoding are subjected to primary simulation decoding; and the scanning signals output through simulation decoding are directly sent to the line scanning lines of the display screen. The driving platform adopted by the invention comprises a coding control unit, a digital decoding unit and a simulation decoding unit. According to the line scanning driving method provided by the invention, through coding, decoding and re-decoding, the driving for the display screen is completed, and the scanning driving for the display screen in optional size and optional driving requirements can be effectively and flexibly realized. According to the driving platform based on the driving method, through the coding, decoding and re-decoding, the pins of the scanning driving signal output by a programmable chip can be greatly reduced, and the flexibility of the scanning driving is maintained, and the development for the high-performance display screen is effectively supported.

The present invention realizes the time domain de-interleaving using embedded eDRAM in a time domain synchronous orthogonal frequency division multiplexing receiver, belonging to de-interleaving domain of digital communication. A receiver having a de-interleave with a processor for processing interleaved data; and a built-in eDRAM coupled to the processor for processing the interleaved data is provided.

The invention provides a soft start circuit used in a monolithic integration switching-type regulator, which comprises a charging current generative circuit which is internally provided with a bias current generator, a soft start capacitor and a group of current mirrors, and is used for generating a first current IREF in the bias current generator, and then the IREF generates charging current ICSSby a group of current mirrors, the ICSS charges the soft start capacitor and generates capacitance voltage on the soft start capacitor; a soft start voltage generative circuit obtains the capacitancevoltage which is taken as the soft start voltage SS to be output; a soft start control signal generative circuit is internally provided with the input end of a comparator which respectively inputs the SS and a first voltage reference VREF, and is used for selecting one of a second reference voltage and the SS as the output voltage according to a high-low output soft start signal control signal SS-signal between the SS and VREF. The technology provided by the embodiment is applied to ensure that the output of the switching-type regulator realizes the smooth transition from the soft start to normal operating conditions, and no external high-capacity soft start capacitor is need, thus reducing chip pins and cost.

The invention provides a system and a method for debugging multiple field-programmable gate arrays (FPGAs). The method comprises the following steps: selecting and grouping to-be-tested signals according to a clock domain by virtue of a signal selection and transmission module for instantiating each to-be-tested FPGA, and configuring a high-speed serial transceiver bus port of signal transmission; performing logic synthesis and location wiring on the design logic of the to-be-tested FPGAs and the signal selection and transmission module together; finding displacement information aligned with all channels according to the longest time delay in high-speed serial bus channels of all the to-be-tested FPGAs by using a special tested FPGA in a channel alignment operating mode selected by a debugging host; and selecting a to-be-tested signal group of the to-be-tested FPGA by the debugging host, and configuring the channel time delay value by using frequency information of the to-be-tested signal group. According to the system and the method disclosed by the invention, the cross-FPGA chip signal is observed and captured by using a special tested FPGA, and the fault tracing and positioning efficiency of a debugging system is improved.

The invention discloses a chip clock source detection circuit which comprises a counter and a comparator, the input end of the counter is connected with the output end of an on-chip oscillation circuit, the output end of the counter is connected with the input end of the comparator, and the output end of the comparator is connected with the selection end of a clock selector; the on-chip oscillation circuit outputs XTO pulses to the counter, 1 is added to the count value of the counter every time one XTO pulse appears, and counting is stopped when the count value is accumulated to a preset value; the comparator compares the count value with a preset value, if the count value is larger than or equal to the preset value, a high level is output, and otherwise, a low level is output. The chip clock source detection circuit provided by the invention is only composed of a small-scale counter and a comparator, and the hardware scale is extremely small; the chip clock source detection circuit is additionally arranged in an original chip, chip clock source selection can be achieved through two pins, the clock source mode can be accurately judged without user configuration, and generation of system clock signals is ensured.

The present invention provides circuit and associated method capable of identifying keys and implementing keypad; the circuit includes a plurality of input nodes and a decoder; each input nodes is associated with multiple keys, and the decoder is capable of distinguishing each of the multiple keys of an input node such that a keypad can be implemented with low pin count.

A high accurate D / A conversion circuit connects its all signal leading out wires to FPGA programmable logic circuit. The prepared circuit gas high D / A conversion accuracy with conversion cipher of 24 positions, harmonic distortion of minus 102dB, dynamic range of 122dB and high S - N ratio since it applies serial input for D / A conversion.

The invention relates to the field of vehicle electronics, in particular to a vehicle-mounted alcohol detecting device with a GPS. According to the vehicle-mounted alcohol detecting device disclosed by the invention, a technical method that the alcohol detecting device is mounted near a steering wheel is adopted, so that the technical problem that a conventional alcohol detecting device is inconvenient to carry along with people is solved, and the technical effect that alcohol detection can be performed at any time is achieved. A technical method that a bluetooth module is used for wireless communications is adopted, so that the technical effect that a mobile device of a driver can be connected with the vehicle, the vehicle can use the positioning function of the GPS is achieved. According to the vehicle-mounted alcohol detecting device disclosed by the invention, a technical method that a GPS module is additionally arranged to position the vehicle is adopted, so that the technical effect that family members of the driver can position the present location of the driver through the GPS can be achieved.

The present application relates to a clock data recovery circuit and a loop adjustment method, the clock data recovery circuit comprising: an LC oscillator for outputting a signal of a predetermined frequency; a first frequency detection module which comprises two input ends, the first frequency detection module is used for outputting driving current according to the frequency difference between signals input by the two input ends, and one input end of the first frequency detection module is connected with the output end of the LC oscillator; and a second frequency detection module, wherein the second frequency detection module comprises a clock input end and a data input end, and is used for outputting a driving current according to a frequency difference between a signal input by the clock input end of the second frequency detection module and a signal input by the data input end of the second frequency detection module. According to the technical scheme provided by the invention, pins of the IC chip can be effectively reduced, and the manufacturing cost of the IC chip is reduced.

The invention discloses electronic equipment and a data interaction method. The electronic equipment comprises a PCH (platform controller hub) unit, an SI / O (super input / output) unit and an I / O extension unit, wherein the SI / O unit is connected with the PCH unit and the I / O extension unit, and the I / O extension unit is provided with at least one I / O interface. When first external equipment is connected with the electronic equipment, the electronic equipment can be communicated with the electronic equipment through a first I / O interface of the I / O interfaces, so that the PCH unit can be in data interaction with the first external equipment through the SI / O unit and the I / O extension unit.

The invention provides an induction cooker. The induction cooker comprises an IGBT driving circuit, an IGBT, a resonance circuit, a control chip, a first resistor, a voltage division element, a second resistor and a first diode; the output pin of the control chip is connected with the connecting point of the first resistor and the voltage division element; and by detecting the voltage value of the connecting point, whether a direct current power supply has fluctuations or not can be judged, so that the driving voltage output by the output end of the control circuit can be determined according to the value of the direct current power supply. One pin is shared for voltage sampling and signal outputting, so that addition of a sampling circuit and a voltage comparison circuit in the induction cooker can be avoided, so that the circuit structure is simplified and the pins of the control chip can be saved, thereby lowering the costs of the control chip and the induction cooker; and the driving voltage output by the output end of the control circuit is determined according to the value of the direct current power supply, so that the IGBT is protected.

The invention relates to an integrated circuit of an improved motorcycle igniter, comprising a power source anode end, a positive impulse input end, a negative impulse input end, a power source cathode end, an ignition control impulse end, a first constant-current output end, a second constant-current output end and a rotate-speed curve forming end. The positive impulse input end, the negative impulse input end and the rotate-speed curve forming end are input ends; the ignition control impulse end, the first constant-current output end and the second constant-current output end are output ends; the power source anode end and the power source cathode end are connected with a corresponding direct-current power source; the output of the ignition control impulse end can drive an ignition angle needed by installing the motorcycle igniter to ignite, and an ignition advanced angle of the motorcycle igniter can be regulated by regulating the rotate-speed curve forming end. The integrated circuit of the improved motorcycle igniter reduces pins of an igniter integrated circuit by optimizing the traditional igniter integrated circuit, greatly reduces the encapsulation cost of the igniter integrated circuit, is convenient to operate and use and is safe and reliable.

The invention provides a NAND FLASH system, a NAND FLASH controller and a data processing method of the NAND FLASH controller. The NAND FLASH system comprises a serial peripheral interface (SPI), the NAND FLASH controller, and a NAND FLASH bare chip, wherein the NAND FLASH controller is connected with the SPI through a serial port, connected with the NAND FLASH bare chip through a parallel port, and used for converting first parallel data inputted by the NAND FLASH bare chip into first serial data and outputting the first serial data through the SPI, as well as converting second serial data inputted by the SPI into second parallel data and outputting the second parallel data to the NAND FLASH bare chip. Through adoption of the NAND FLASH system, the NAND FLASH controller and the data processing method, the difficulty in communication between the NAND FLASH bare chip and electronic equipment as well as the volume occupied by the NAND FLASH bare chip can be reduced.

The invention provides an over-voltage protection circuit applied to a boost switching power, which consists of a bleeder circuit and a voltage comparator. The voltage comparator compares an output voltage and a reference voltage of the bleeder circuit and then sends the voltages into a control logic circuit for obtaining a controlling signal. The over-voltage protection circuit further includes a sampling voltage reducing circuit. An input end of the sampling reducing circuit is connected with a drain electrode of switching power and an output end of the sampling reducing circuit is connected with an input end of the bleeder circuit. Therefore the drain electrode of the switching power is sampled and the voltage is reduced. The over-voltage protection circuit in the invention, compared with other over-voltage protection methods, adopts a reverse breakdown voltage of a diode as a condition for detecting whether over voltage occurs, thus realizing the simple structure with low cost. Through an SW pin, the output voltage is detected; therefore, the judgment of whether over voltage occurs by detecting a VOUT pin is avoided, thus reducing the exterior pins of a chip and saving the encapsulation cost.