The invention discloses a 
wafer level 
chip size 
package and a manufacturing method of the 
wafer level 
chip size 
package, belonging to the field of sensors. The 
wafer level 
chip size 
package comprises a wafer, wherein the positive surface of the wafer is a first surface which forms an 
image sensing region, the negative surface of the wafer is a second surface, and the first surface comprises a 
microlens, a 
metal interconnection layer and an 
optical interaction region from top to bottom; a 
silicon through hole which does not penetrate through a 
silicon substrate and a redistribution region are manufactured on the first surface, and I / Os at the periphery of the 
optical interaction region are connected with the 
silicon through hole; the wall of the silicon through hole is manufactured into a 
passivation layer and is filled; a 
polymer material is manufactured into a second protective layer on the redistribution region; the first surface is in bonding with a 
glass sheet, and a cavity is formed between the 
glass sheet and the wafer; the second surface is thinned and forms a groove structure through an 
etching process, and the silicon through hole is exposed; a line layer is manufactured on the second surface, and the silicon through hole is connected to a solder pad 
cushion; a 
welding prevention layer is manufactured on the line layer, and the solder pad 
cushion is exposed; and a 
solder ball is arranged on the solder pad 
cushion. With the adoption of the wafer level 
chip size package and the manufacturing method of the wafer level 
chip size package, the technological process is reduced, the reliability and the production efficiency of a product are improved, and the production cost is lowered.