The invention relates to methods for manufacturing 
semiconductor devices. Processes are disclosed for implementing suspended 
single crystal silicon nano wires (NWs) using a combination of anisotropic and isotropic etches and spacer creation for sidewall protection. The core dimensions of the NWs are adjustable with the integration sequences: they can be triangular, rectangular, quasi-circular, or an alternative polygonal shape. Depending on the length of the NWs, going from the sub-micron to 
millimeter range, the NWs may utilize support from anchors to the side, during certain 
processing steps. By changing the lithographic dimensions of the anchors compared to the NWs, the anchors may be reduced or eliminated during 
processing. The method covers, among other things, the integration of Gate-All-Around NW (GAA-NW) MOSFETs on a bulk 
semiconductor. The GAA structure may consist of a 
silicon core fabricated as specified in the invention, surrounded by any 
usable gate dielectric, and finally by a gate material, such as polysilicon or 
metal. The source and drain of the GAA-NW may be connected to the bulk 
semiconductor to avoid 
self heating of the device over a wide range of operating conditions. The GAA-NW 
MOS capacitor can also be used for the integration of a Gate-All-Around 
optical phase modulator (GAA modulator). The working principle for the 
optical modulator is modulation of the 
refractive index by 
free carrier accumulation or inversion in a MOS capacitive structure, which changes the phase of the propagating light.